1. Field of the Invention
The invention relates generally to memory systems, and more particularly to systems and methods for reducing the time required to transfer data from one memory cell to another by avoiding the routing of the data through a processor or other memory controller.
2. Related Art
As the desire for faster and more powerful computing systems drives the development of new technologies, older technology is rapidly become less useful and even obsolete. Recent processors operate at faster clock speeds than ever before, and memory systems are capable of providing huge amounts of storage for data. As these processors access these large memories, however, the latency of the data in the memories is increasingly becoming a problem.
While the speed at which the memory systems operate has not decreased, in many instances it has not kept pace with increases in processor speed. This situation has been aggravated by the fact that, with faster processors and more available memory, more data transfers are typically performed by current systems than in earlier systems. For instance, current applications commonly make many data transfers from one memory location to another.
While it may appear that data transfers from one memory location to another should not take any appreciable amount of time, this is not the case. Conventionally, these data transfers involve reading data from one memory location into a processor register, and then writing the data from the register back into a different memory location. When viewed more closely, the process of simply getting the data from the memory location to the processor register alone conventionally involves, the data being read from a memory cell by first sense amplifier, the output of the first sense amplifier being read by a second sense amplifier, the output of the second sense amplifier being written into an I/O buffer, the data being read from the I/O buffer into a cache memory (or, typically, several successive levels of cache memories,) and then the data being read into the processor register. The process of getting the data from the register to the second memory location involves the reverse of this process. Thus, the origin of data latency in a simple memory-to-memory data transfer becomes more evident.
Because the latency of these types of memory-to-memory data transfers is becoming larger in comparison to other processing tasks, it would be desirable to provide a means to reduce latency in these types of transfers.